One of the last steps in the fabrication of silicon integrated circuits (ICs) establishes the electrical connections between the circuitry formed in the silicon IC chip and the other electrical components in the electronic system of which the IC chip is a part. Older technology utilized wire bonding between pads on the IC chip and an IC package having multiple connection pins, which were fixed to a printed circuit board (PCB) and electrically connected to a wiring pattern on the PCB. Typically, the IC package pins were directly soldered to the wiring pattern on the PCB or were reversibly inserted into IC sockets soldered to the board.
Wire bonding is a lengthy serial process even when automated. Inserting IC packages onto the PCB is a process that is not easily automated. Accordingly, a preferred process at the present time includes flip chip bonding involving under bump metallization (UBM) in which the active side of the IC chip is directly bonded to the electrical circuit on the PCB or other supporting substrate through solder bumps deposited either on the chip or the supporting substrate.
An example of a conventional flip chip bonding technique will be described with reference to the cross-sectional view of FIG. 1. An integrated circuit chip 10 is form in a silicon wafer 12 is processed according to well known techniques to develop a replicated pattern of integrated circuits in a device layer 14 of the wafer 12. Although a monocrystalline silicon wafer is most common, the invention is equally applicable to silicon layers formed on other substrates, such as SOI(silicon on insulator) wafers. Typically, the bottommost active sub-layer in the device layer 14 includes the semiconductor circuitry whether it be logic or memory. For advanced integrated circuits, there may be billions of semiconductor devices formed in the active sub-layer. The upper sub-layers typically include multiple layers of metallizations, five metallization layers are not unusual, to interconnect the large number of active areas and to connect to the outside electrical lines, whether for input, output, or power. The uppermost metallization layer includes a substantial number of contact pads 16, which are typically formed at the same time as horizontal and perhaps vertical interconnection lines in the uppermost metallization level. The uppermost metallization level may include not only the contact pads 16 but also some horizontal interconnects composed of the same metal as the pads 16. For aluminum metallization, the pads 16 are formed in the final metallization level by aluminum sputter deposition. For copper metallization, the pads 16 are typically formed in the final metallization level by copper electroplating. The contact pads 16 have a relatively large lateral extent, for example, to 20 or 50 to 100 μm but a depth of only about 0.2 to 2 μm, a depth typical for metallization layers. It is understood that the typical processing is performed at the wafer level. There may be tens to hundreds of contact pads 16 for each chip and on the order of hundreds of chips for each wafer. Therefore, the described steps can be efficiently performed in parallel at the wafer level prior to dicing the wafer into separate integrated circuits.
A dielectric layer 18, typically composed of a polymeric spin-on glass or plasma deposited nitride or oxynitride, electrically isolates the multiple contact pads 16. A planar UBM (under bump metallization) layer 20 is then deposited and photolithographically defined. Solder balls 22 are deposited over the UMB layer 20, typically by electroplating or printing through a mask although but pulsed lasers have been used to locally melt a solder wire. A solder reflow is performed to cause the solder bump 22 to react with and contact to the UMB layer 20. The reflow anneal step further causes the solder to form into a ball-shaped solder bump 26 as illustrated.
The fabrication technique described above is illustrative only. There are many known techniques for depositing and defining the areas of the metallization and the solder bump, for example, as described by Degani in U.S. Pat. No. 5,904,859 and by Munroe et al. in U.S. Pat. No. 6,107,180, both incorporated herein by reference in their entireties.
At this point, the wafer is usually diced into the multiple integrated circuit dice, each die or chip including tens to hundreds of the illustrated contact pads 16. The contact pads 16 may be arranged around the periphery of the active area of the chip or may be arranged in a multi-row pattern over most of the top layer of the chip. As illustrated in the cross-sectional view of FIG. 2, the chip 10 is inverted and its bumps 26 are aligned with and pressed against corresponding contact pads 28 in a PCB or other support substrate 30 at an elevated temperature in what amounts to another reflow in which the solder reacts with both the substrate 30 and the contact pads 28. The pads 28 are typically composed of copper or nickel overlying the copper metallization of the PCB. The substrate contact pads 28 provide not only mechanical support but also electrical contact to the electrical PCB interconnection pattern because of the reasonable electrical conductivity of the UBM layer 20 and the solder bump 22.
There are many forms for the PCB board 30 and its metallization 28. Often the PCB board contains multiple levels of wiring, each having its own metallization 28. Often vias are formed partially or completely through the PCB board and the metallization 28 may coat the side or bottom of vias. The solder 22 can reflow into vias to complete the electrical contacts in or through the vias.
The UBM layer 20 may include multiple sub-layers since it performs several different functions. It needs to provide adequate wetting and adhesion between the UBM layer 20 and both the solder 22 and the final metal layer of the contact pad 16. Importantly, it needs to act as a barrier layer. The solder 22 typically consists of heavy metals including tin and lead. Such heavy metal should be prevented from diffusing into the metallization 16 and possibly down to the active silicon layer.
In the past, the solder layer 22 was formed of a eutectic lead-tin (PbSn) alloy having a composition of approximately 63 wt % tin and 37 wt % lead. The eutectic PbSn has the advantage of a low melting temperature of about 183° C., which allows the solder reflow to be typically performed at 210 to 220° C. However, lead is now widely disfavored because of its environmental and general medical effects incurred during the IC fabrication and in the disposal of the increasing amount of toxic electronic waste. Europe and Japan have already implemented strict standards and are debating imposing bans against lead-containing solder. The U.S. is expected to impose restrictions by 2006. As a result, much effort has been expended in developing a lead-free or at least reduced-lead solder typically having a higher tin content. Heretofore, however, the lead-free solders have introduced substantial difficulties with the barrier layer. The difficulties have been complicated by the switch from aluminum to copper metallization in the semiconductor chips.
Nickel is generally perceived as being the preferred barrier material as Cook et al. described for a nickel-containing UBM in U.S. Pat. No. 5,719,070. Nickel however presents difficulties when it is deposited by magnetron sputtering since its magnetic permeability limits the nickel target to be relatively thin because the target shunts the magnetic field from the magnetron and hence is not preferred for commercial use. Wet electroless plating has been used to deposit 10 to 20 μm films of Ni(P) (nickel doped with phosphorous) as the barrier layer in addition to a gold wetting and passivation layer. Such a barrier layer tends to be insufficiently dense and be subject to formation of voids due to Ni3P recrystalllization. NiV barrier layers have been quite useful with PbSn solders in a Al/NiV/Cu trilayer with the Cu protecting the NiV from the solder. This combination is especially useful because NiV with 7 wt % of V is non-magnetic, thus promoting its deposition by magnetron sputtering. However, for Sn-rich Pb-free solders, NiV/Cu introduces difficulties. Copper and tin readily form an intermetallic compound so that the Cu is quickly dissolved and exposes the NiV layer subject to tin diffusion.
Generally, the barrier layer and associated sub-layers should react relatively slowly with the solder. Otherwise, the solder breaches the barrier layer and its tin or other fast-diffusing heavy metal component is directly exposed to the metallization.
A further consideration is that the UBM layer is preferred to exhibit compressive stress rather than tensile stress. Residual tensile stress tends to make it difficult to bond the chip and to cause peeling of the processed layers from the wafer substrate. Conventionally, tensile stress in NiV films has been reduced, as illustrated by plot 40 in the graph of FIG. 3, by increasing the amount of RF bias power applied to the pedestal electrode supporting the wafer in a magnetron sputter reactor. Although wafer biasing is effective, it narrows the process window and the biasing introduces the possibility of damaging the film by bombardment of energetic ions on the biased wafer.